1. Field of the Invention
The present invention relates to coaxial connectors and, in particular, to coaxial connectors used for connecting single chip and multichip modules to each other and to printed circuit boards.
2. Description of Related Art
In surface mount technology, integrated circuits (ICs) are connected to ceramic or organic packages which in turn have metal leads extending therefrom for connection to a printed circuit (PC) board by means of soldering or by insertion into a socket. The electrical attachment of the IC to the package is often referred to as the first level of attachment. The electrical attachment of the package to the PC board is the second level of attachment. The trend for IC packages is to increase the density and number of ICs on a package with a resultant increase in the number of Input/Output (I/O) connections at the second level of attachment.
The density of the second level attach for high IO counts is currently being satisfied by several types of attachment schemes including Pin Grid Arrays (PGAs), Ball Grid Arrays (BGAs) and Column Grid Arrays (CGAs).
The PGA consists of an array of metal pins which are typically 100 to 200 mils long and are plated with gold to improve resistance to oxidation. The PGA is attached to circular conductive or metallized pads on the package. Attachment is typically by soldering or brazing to the metallized pads arranged on the package surface surrounding the ICs or on the opposite side of the package from the ICs. The metallized pads are electrically connected to internal conductors or vias which are used to provide wiring for the ICs. The PGA connection method has been used for many years and allows the IC and package to be tested or burned-in prior to installation in a product since the pins can be socketed and tested easily and with minimal disruption of the structure of the package. The long pins also help to absorb the difference in Coefficient of Thermal Expansion (CTE) between the package and the circuit board. A large CTE mismatch can cause failure of the solder at the package to pin location. Long lead lengths help to minimize the lateral movement of the pins at the solder joints. The pad diameter required to provide a reliable solder attach of the pins consumes a large amount of surface area on the package making an increase in the IO density of the second level attach difficult. Typical IO pitch between the pins is about 100 mils. In addition, the long pin lead lengths contribute greatly to an unwanted inductance between adjacent pins which causes considerable degradation of electrical performance. In order to help minimize crosstalk, traditional wiring schemes surround signal conducting pins with ground or voltage pins that can help to isolate the pins. The isolation schemes cause further loss in IO density and performance. Additionally, off chip frequencies are increasing into the GHz range demanding greater isolation of the signal conductors from unwanted crosstalk.
Another second level attach method is the Ball Grid Array (BGA). The BGA uses a pad attach scheme similar to the PGA except, instead of a metal pin, a high temperature solder ball is attached to the pad using a lower temperature solder. The resultant ball grid array provides a higher density of IO with a typical pitch of 40 to 50 mils. The shorter height of the balls, typically 35 mils, greatly decreases the contribution of the interconnection length to unwanted inductance. However, the shorter ball height makes the BGAs poor candidates for a pluggable burn-in test or for a pluggable package for system use and field upgrades because the balls are made of soft solder specifically for ease of attachment and absorption of stresses of CTE mismatch between the package and the board. The soft solder of the BGA deforms easily and can permit contact degradation over repeated thermal cycles. Another drawback of the BGA is the short height of the balls which have little resistance to solder fatigue caused by numerous thermal cycles. Resistance to fatigue is important to packages of larger size since the IO connections at the greatest distance from the center of the packages, usually the corners, are the most likely to fail. A compromise solution to this problem has been the introduction of the Column Grid Array (CGA) package. Again, an array of pads are connected to a higher joining temperature solder, this time in the form of a column or wire, by a lower joining temperature solder. The pitch of a CGA connection can be the same as a BGA. The columns provide a higher degree of reliability compared to the BGA due to their longer lengths. However, the columns are not easily pluggable for burn-in or system or field upgrades. In addition, the solder columns are very easily damaged in processing and handling and must be protected at all times.
One approach to the signal isolation problem is U.S. Pat. No. 5,266,912 which describes a coaxial connector which requires a through-hole in the substrate which takes up surface area on both sides of the substrate. The device has less than desired attachment flexibility because there is no opportunity to reset the grid during attachment of the pins in the coaxial connectors. Resetting the grid would assure that the pins are properly spaced after connection. Also, there is no mechanism for a wiping action between the pin and the socket of the mating coaxial connector which would increase the reliability of the pluggable connection.
An ideal second level connection scheme would allow high density IO, pluggable burn-in, pluggable field replacement, low inductance, high signal isolation and high reliability.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an electronic interconnect device which is compliant in the XY axis thereby allowing for insertion into a socket while being tolerant of socket to package movement during thermal cycling due to CTE mismatch.
A further object of the invention is to provide a coaxial connector attachment scheme by which an array of compliant connectors arranged on a package can be aligned during insertion into a socket which can also be used to carry voltage or ground.
It is yet another object of the present invention to provide a compliant array of connectors which can be mass produced.
It is yet another object of the present invention to provide a compliant array of electronic interconnect devices which are suitable for high frequency applications.
It is yet another object of the present invention to provide an electronic interconnect device array which can be plugged into a test socket and system board for burn-in and assembly.
It is yet another object of the present invention to provide a coaxial connector with high IO density.
Still other objects and advantages will in part be obvious and will in part be apparent from the specification.